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| apr. 2008 flexible step-down switching regulator overview features 1) 2) 3) 4) 5) 6) 8) 9) 10) 11) 12) 13) 14) 15) minimal external components wide input voltage range: 7 v to 35 v (bd9778f/hfp and bd9781hfp), 7 v to 48 v (bd9001f) built-in p-ch power mos fet output voltage setting enabled with external resistor: 1 to v in reference voltage accuracy: 2% wide operating temperature range: -40?c to +125?c (bd9778f/hfp and bd9781hfp), -40?c to +95?c (bd9001f) low dropout: 100% on duty cycle standby mode supply current: 0 a (typ.) (bd9778f/hfp and bd9781hfp), 4 a (typ.) (bd9001f) oscillation frequency variable with external resistor: 50 to 300 khz (bd9001f), 50 to 500 khz (bd9778f/hfp and bd9781hfp) external synchronization enabled (only on the bd9781hfp) soft start function : soft start time fixed to 5 ms (typ.)) built-in overcurrent protection circuit built-in thermal shutdown protection circuit high power hrp7 package mounted (bd9778hfp and bd9781hfp) compact sop8 package mounted (bd9778f and bd9001f) all fields of industrial equipment, such as flat tv , printer, dvd, car audio, car navigation, and communication such as etc, av, and oa. applications product lineup technical note bd9778f/hfp, bd9001f, bd9781hfp single-chip built-in fet type switching regulator series the flexible step-down switching regulator controller is a switching regulator controller designed with a high-withstand-voltag e built-in power mos fet, providing a free setting function of operating frequency with external resistor. this switching regulat or controller features a wide input voltage range (7 v to 35 v or 7 v to 48 v) and operating temperature range (-40?c to +125?c or -40?c to +95?c). furthermore, an external synchronization input pin (bd9781hfp) enables synchronous operation with external clock. bd9778f/hfp 2a 7v ~ 35v 50 ~ 500khz not provided provided - 40?c ~ +125?c sop8 / hrp7 output current input range oscillation frequency range external synchronization standby function operating temperature package bd9001f 2a 7v ~ 48v 50 ~ 300khz not provided provided - 40?c ~ +95?c sop8 bd9781hfp 4a 7v ~ 35v 50 ~ 500khz provided provided - 40?c ~ +125?c hrp7 item
absolute maximum ratings(ta = 25?c) 2/16 recommended operating range electrical characteristics *1 should not exceed pd-value. *2 reduce by 44mw/c over 25c, when mounted on 2-layer pcb of 70 70 1.6 mm3. (pcb incorporates thermal via. copper foil area on the front side of pcb: 10.5 10.5 mm2. copper foil area on the reverse side of pcb: 70 70 mm2) *3 reduce by 5.52 mw/c over 25c, when mounted on 2-layer pcb of 70 70 1.6 mm3. output switch pin voltage output switch current bd9778f/hfp,bd9781hfp bd9778f/hfp,bd9781hfp bd9778f/hfp, bd9001f bd9001f bd9001f bd9781hfp hrp7 sop8 power dissipation parameter symbol unit v en/sync, v en v rt, v fb, v inv a p d limits 5.5 0.69 v in 2 en/sync, en pin voltage v in v sw i sw 50 w t opr t stg t jmax - 40 ~ +95 - 40 ~ +125 - 55 ~ +150 ?c ?c ?c power supply voltage operating temperature range v in 36 v v v *1 4 *1 *2 *3 rt, fb, inv pin voltage storage temperature range maximum junction temperature 7 150 bd9778f/hfp 7 ~ 35 ~ 2 6 ~ 100 50 ~ 500 40 ~ 800 parameter operating power supply voltage output switch current output voltage (on duty) oscillation frequency oscillation frequency set resistance bd9001f 7 ~ 48 ~ 2 6 ~ 100 50 ~ 300 100 ~ 800 bd9781hfp 7 ~ 35 ~ 4 6 ~ 100 50 ~ 500 39 ~ 800 unit v a % khz k possible operating range bd9778f/hfp 5 ~ 35 parameter operating power supply voltage bd9001f 7 ~ 48 bd9781hfp 5 ~ 35 unit v bd9778f/hfp (unless otherwise specified, ta = -40?c to +125?c, v in =13.2 v, v en = 5 v) circuit current standby circuit current reference voltage 2 reference voltage 1 [error amp block] reference voltage input regulation input bias current maximum fb voltage parameter limits typ. min. max. 0.96 - - - operating output current of overcurrent protection 2 - symbol i olimit i oleak v ref2 v ref1 ?v ref i q i stb r on i b v fbh v fbl i fbsink i fbsource t ss f osc v en i en ?f osc - 1 2.4 70 - - 82 - 0.8 - condition v en =5v v fb =v inv v fb =1.5v,v inv =1.5v v fb =1.5v,v inv =0.5v khz v in =5 ~ 35v v in =5 ~ 35v v inv =1.1v v inv =0.5v v inv =1.5v v in =35v,v en =0v v en =0v,ta=25?c i o =0a i sw =50ma * design assurance * design assurance output leak current [sw block] power mos fet on resistance minimum fb voltage fb sink current fb source current soft start time [oscillator block] oscillation frequency frequency input regulation [enable block] threshold voltage sink current - - 5.0 unit a a a v % ma a v v ma a ms r t =390k v a % 1.00 3 0.53 4 0.5 - 2.5 120 0.05 5 102 1 1.7 13 0 0 - 3.0 1.04 0.98 v fb =v inv ,ta=25?c v 1.00 1.02 4.2 10 0.9 - - - - 170 0.10 - 122 - 2.6 50 30 - 0.5 * not designed to be radiation-resistant. 3/16 bd9781hfp (unless otherwise specified, ta= - 40?c ~ +125?c,v in =13.2v,v en/sync =5v) parameter symbol i olimit i oleak v ref2 v ref1 ?v ref i q i stb r on i b v fbh v fbl i fbsink i fbsource t ss f osc v en/sync i en/sync f sync ?f osc condition unit a a v % ma a v v ma a ms khz v a khz % v en/sync =5v v en/sync =0v,ta=25oc f en/sync =150khz v fb =v inv v fb =1.5v,v inv =1.5v v fb =1.5v,v inv =0.5v r t =390k v in =5 ~ 35v v in =5 ~ 35v v inv =1.1v v inv =0.5v v inv =1.5v v in =35v,v en/sync =0v i o =0a i sw =50ma * design assurance * design assurance [enable/synchronizing input block] threshold voltage sink current external synchronizing frequency limits typ. min. max. 0.97 - - 4 - - 1 2.4 70 - - 82 - 0.8 - - - - 5.0 1.00 3 0.5 8 0.5 - 2.5 120 0.05 5 102 1 1.7 35 150 0 - 3.0 1.03 vv fb =v inv ,ta=25oc 0.98 1.00 1.02 8 0.9 - - - - 170 0.10 - 122 - 2.6 90 - 30 a - 010 - 0.5 bd9001f (unless otherwise specified, ta= - 40?c ~ +95?c,v in =13.2v, v en =5v) [enable block] threshold voltage sink current circuit current standby circuit current reference voltage 2 reference voltage 1 [error amp block] reference voltage input regulation input bias current maximum fb voltage parameter operating output current of overcurrent protection v en i en symbol i olimit v ref2 v ref1 ?v ref i q i stb r on i b v fbh v fbl i fbsink i fbsource ts s f osc ?f osc condition v a unit a v v % ma a a v v ma ms a khz % v fb =v inv v fb =1.5v,v inv =1.5v v fb =1.5v,v inv =0.5v r t =390k v in =7 ~ 48v v in =7 ~ 48v v en =5v v inv =1.1v v inv =0.5v v inv =1.5v i o =0a i sw =50ma * design assurance * design assurance [sw block] power mos fet on resistance minimum fb voltage fb sink current fb source current soft start time [oscillator block] oscillation frequency frequency input regulation 0.8 1.7 13 2.6 50 limits typ. min. max. 0.96 0.98 - - - 2.5 - - 1 2.4 70 - - 82 - - - 5.0 1.00 3 0.6 4 0.5 - 2.5 120 5 0.05 102 2 - 3.0 1.04 1.00 1.02 4.2 410 1.2 - - - - - 170 0.10 122 - - 0.5 * not designed to be radiation-resistant. * not designed to be radiation-resistant. circuit current standby circuit current reference voltage2 reference voltage1 [error amp block] reference voltage input regulation input bias current maximum fb voltage operating output current of overcurrent protection output leak current [sw block] power mos fet on resistance minimum fb voltage fb sink current fb source current soft start time [oscillator block] oscillation frequency frequency input regulation v en =0v,ta=25?c v fb =v inv ,ta=25?c 4/16 reference data fig.1 output reference voltage vs. ambient temprature (all series) fig.2 frequency vs. ambient temperature (all series) fig.3 standby current (bd9781hfp) fig.5 standby current (bd9001f) fig.6 circuit current (bd9781hfp) fig.8 circuit current (bd9001f) fig.9 on resistance v in =5v (bd9781hfp) fig.11 on resistancev in =13.2v (bd9781hfp) 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 -25 -50 0 25 50 75 100 ambient temperature : ta[] reference voltage : v ref [v] 125 0 100 200 300 400 500 600 -25 -50 0 25 50 75 100 ambient temperature : ta[] oscillating frequency : fosc[khz] 125 910k 91k 390k 39k 0 1 2 3 4 5 6 7 8 9 10 5 0101520253040 input voltage : v in [v] stand-by current : i stb [a] 35 125 v cc =12v istb=0.14a 25 125 25 C40 -40 fig.7 circuit current (bd9778f/hfp) 1 0 5 0101520253040 input voltage : v in [v] circuit current : i cc [ma] circuit current : i cc [ma] 35 2 3 4 from the top, - 40 25 125 from the top, - 40 25 125 1 0 5 0101520253040 input voltage : v in [v] circuit current : i cc [ma] stand-by current : i stb [a] 35 2 3 4 fig.10 on resistance v in =7v (bd9781hfp) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.5 0.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 output current : i o [a] fet on resistance : r on [] ta=25 ta=125 ta=-40 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.5 0.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 output current : i o [a] fet on resistance : r on [] ta=25 ta=125 ta=-40 4.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.5 0.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output current : i o [a] fet on resistance : r on [] ta=25 ta=125 ta=-40 fig.4 standby current (bd9778f/hfp) 5 0101520253040 35 input voltage : v in [v] input voltage : v in [v] input voltage : v in [v] 0 1 2 3 4 5 6 7 8 9 10 stand-by current : i stb [a] 125 25 -40 v cc =12v istb=0.14a 60 60 50 40 30 20 10 0 10 20 30 40 50 40 30 20 10 0 1 2 3 4 from the top, 125 - 40 25 fig.12 on resistance v in =5v (bd9778f/hfp) output current : i o [a] 0.5 0.0 1.0 1.5 2.0 2.5 fet on resistance : r on [] ta=-40 ta=25 ta=125 5/16 output current : i o [a] 10 20 30 40 50 60 70 80 90 100 0 0 0.5 1.0 conversion efficiency [%] 1.5 2.0 5v output 3.3v output fig.18 i o vs efficiency(v in =12v,f=100khz) ? (bd9778f/hfp) 0 1 2 3 4 5 6 output voltage : v o [v] 1 02345 output current : i o [a] ta=25 ta=125 ta=-40 fig.21 current capacitance(v in =12v,vo=5v,f=100khz) (bd9778f/hfp) 0 1 2 3 4 5 6 1 0234567 output current : i o [a] output voltage : v o [v] ta=25 ta=125 ta=-40 fig.20 current capacitance(v in =12v,vo=5v,f=100khz) (bd9781hfp) 0 1 2 3 4 5 6 1 02345 output current : i o [a] output voltage : v o [v] ta=25 ta=125 ta=-40 fig.22 current capacitance(v in =12v,vo=5v,f=100khz) (bd9001f) fig.16 on resistance v in =13.2v (bd9001f) fig.19 i o vs efficiency(v in =12v,f=100khz) ? (bd9001f) 0 0.4 0.8 1.2 1.6 2 output current : i o [a] conversion efficiency [%] 5v output 3.3v output 2.5v output 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 fig.14 on resistance v in =13.2v (bd9778f/hfp) fig.15 on resistance v in =7v (bd9001f) 0.5 0.0 1.0 1.5 2.0 2.5 output current : i o [a] fet on resistance : r on [] ta=25 ta=125 ta=-40 0 0.5 1 1.5 2 2.5 output current : i o [a] fet on resistance : ron[] ta=25 ta=125 ta=C40 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 fig.13 on resistance v in =7v (bd9778f/hfp) output current : i o [a] 0.5 0.0 1.0 1.5 2.0 2.5 fet on resistance : r on [] ta=25 ta=125 ta=-40 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 0.5 1 1.5 2 2.5 output current : i o [a] fet on resistance : ron[] ta=25 10 20 30 40 50 60 70 80 90 100 0 ta=125 ta=C40 2.5v output 1.5v output 10 20 30 40 50 60 70 80 90 100 0 conversion efficiency [%] output current : i o [a] fig.17 i o vs efficiency(v in =12v,f=200khz) ? (bd9781hfp) 0.5 0.0 1.0 1.5 2.0 2.5 3.0 3.3v output 2.5v output 5v output 6/16 block diagram / application circuit / pin assignment (bd9001f) fig.26 fig.25 no. 1 2 3 4 5 6 7 fin pin name v in sw rt gnd fb inv en/sync - fig.23 no. 1 2 3 4 5 6 7 8 function power supply input output error amp output output voltage feedback enable frequency setting resistor connection ground power system power supply input pin name v in sw fb inv en rt gnd pv in fig.24 no. 1 2 3 4 5 6 7 fin pin name v in sw fb gnd inv rt en - (bd9778f) (bd9781hfp) (bd9778hfp) 3 vref 220f 1f 33h 330f 390k 0.1f 4700pf 10k 23k 1 8 - + + - + 4 soft start osc driver latch tsd - + 6 2 on/off 5 7 en l:off h:on v in pv in inv error amp reset sw v o gnd current limit vref fb rt pwm comparator v in inv sw fb v in gnd rt en pvin en rt inv gnd fb sw v in en/sinc inv fb gnd rt sw v in 150k 3 vref 1 - + + - + 5 soft start osc driver latch tsd - + 6 2 on/off 7 4 en l:off h:on v in inv error amp reset sw v o gnd current limit vref fb rt pwm comparator v in 220f 1f 33h 330f 390k 0.1f 4700pf 10k 23k 150k 5 vref 1 - + + - + 6 soft start osc driver latch tsd - + 3 2 sync on/off 7 4 en/ sync l:off h:on v in inv error amp reset sw v in v o gnd current limit vref fb rt pwm comparator 220f 1f 33h 330f 390k 0.1f 4700pf 10k 23k 150k function power supply input output error amp output ground output voltage feedback frequency setting resistor connection enable ground function power supply input output frequency setting resistor connection ground error amp output output voltage feedback enable/synchronizing pulse input ground 3 vref soft start 8 - + + - + 4 osc driver latch tsd - + 6 1 7 inv error amp reset sw v o v in gnd current limit vref v in fb rt pwm comparator inv n.c. fb sw gnd rt en v in 220f 1f 33 h 330f 390k 0.1f 4700pf 10k 23k 150k no. 1 2 3 4 5 6 7 8 ?????? function output non connection error amp output output voltage feedback enable frequency setting resistor connection ground power supply input pin name sw n.c. fb inv en rt gnd v in 7/16 description of operations n error amp the error amp block is an error amplifier used to input the reference voltage (1 v typ.) and the inv pin voltage. the output fb pin controls the switching duty and output voltage vo. these inv and fb pins are externally mounted to facilitate phase compensation. inserting a capacitor and resistor between these pins enables adjustment of phase margin. (refer to recommended examples on page 11.) n soft start the soft start block provides a function to prevent the overshoot of the output voltage vo through gradually increasing the normal rotation input of the error amplifier when power supply turns on to gradually increase the switching duty. the soft start time is set to 5 msec (typ.). n on/off(bd9778f/hfp,bd9781hfp) setting the en pin to 0.8 v or less makes it possible to shut down the circuit. standby current is set to 0 a (typ.). furthermore, on the bd9781hfp, applying a pulse having a frequency higher than set oscillation frequency to the en/sync pin allows for external synchronization (up to +50% of the set frequency). n pwm comparator the pwm comparator block is a comparator to make comparison between the fb pin and internal triangular wave and output a switching pulse. the switching pulse duty varies with the fb value and can be set in the range of 0 to 100%. n osc(oscillator) the osc block is a circuit to generate a triangular wave that is to be input in the pwm comparator. connecting a resistor to the rt pin enables setting of oscillation frequency. n tsd(thermal shut down) in order to prevent thermal destruction/thermal runaway of this ic, the tsd block will turn off the output when the chip temperature reaches approximately 150?c or more. when the chip temperature falls to a specified level, the output will be reset. however, since the tsd is designed to protect the ic, the chip junction temperature should be provided with the thermal shutdown detection temperature of less than approximately 150?c. n current limit while the output power p-ch mos fet is on, if the voltage between drain and source (on resistance load current) exceeds the reference voltage internally set with the ic, this block will turn off the output to latch. the overcurrent protect ion detection values have been set as shown below: bd9781hfp . . . 8a(typ.) bd9001f,bd9778f/hfp . . . 4a(typ.) furthermore, since this overcurrent protection is an automatically reset, after the output is turned off and latched, the latch will be reset with the reset signal output by each oscillation frequency. however, this protection circuit is only effective in preventing destruction from sudden accident. it does not support for the continuous operation of the protection circuit (e.g. if a load, which significantly exceeds the output current capacitance, is normally connected). furthermore, since the overcurrent protection detection value has negative temperature characteristics, consider thermal design. 8/16 timing chart (bd9781hfp) - while in basic operation mode - while in overcurrent protection mode fb v in sw en/sync internal osc fig.27 fig.28 external synchronizing function (bd9781hfp) in order to activate the external synchronizing function, connect the frequency setting resistor to the rt pin and then input a synchronizing signal to the en/sync pin. as the synchronizing signal, input a pulse wave higher than a frequency determined with the setting resistor (rt). on the bd9781hfp, design the frequency difference to be within 50%. furthermore, set the pulse wave duty between 10% and 90%. fig.29 f sync internal osc : for rt only : for external synchronization output short circuit fb sw i o internal osc auto reset auto reset auto reset auto reset 9/16 description of external components design procedure calculation example vo = output voltage, vin (max.) = maximum input voltage io (max.) = maximum load current, f = oscillation frequency 1. setting or output voltage output voltage can be obtained by the formula shown below. v o =1 x (1+r1/r2) use the formula to select the r1 and r2. furthermore, set the r2 to 30 k or less. select the current passing through the r1 and r2 to be small enough for the output current. 2. selection of coil (l) the value of the coil can be obtained by the formula shown below: l=(v in - v o ) x v o / (v in x f x ?i o ) ?i o: output ripple current f = operating frequency ?io should typically be approximately 20 to 30% of io. 3. selection of output capacitor (co) the output capacitor can be determined according to the output ripple voltage ?vo (p-p) required. obtain the required esr value by the formula shown below and then select the capacitance. when v in = 13.2 v, vo = 5 v, io = 2 a, and f = 100 khz, l=(13.2 - 5) x 5/13.2 x 1/100k x 1/(2 x 0.3) =51.8h 47 v in =13.2v, vo=5v, l=100h, f=100khz ?il=(13.2-5) x 5/(100 x 10 -6 x 100 x 10 3 x 13.2) 0.31 when vo = 5 v and r2 = 10 k , 5=1 x (1+r1/10k) r1=40k l=47 h fig.30 v in rt ss sw inv fb gnd c t c in di c o + v o v in c c r c c l r1 r2 r t c ss 3.5m x (i limit -io(max)) vo c max = c max =3.5m x (2-1)/5 =700 ?il=0.31a c max= 700f if this coil is not set to the optimum value, normal (continuous) oscillation may not be achieved. furthermore, set the value of the coil with an adequate margin so that the peak current passing through the coil will not exceed the rated current of the coil. i l imit:2a(bd9778f/hfp,bd9001f), 4a(bd9781hfp) if this capacitance is not optimum, faulty startup may result. (3.5m is soft start time(min.)) when i limit : 2 a, io (max) = 1 a, and vo = 5v, ?il=(v in -v o ) x v o /(l x f x v in ) ?vpp=?il x esr+(?il x vo)/(2 x co x f x v in ) set the rating of the capacitor with an adequate margin to the output voltage. also, set the maximum allowable ripple current with an adequate margin to ?il. furthermore, the output rise time should be shorter than the soft start time. select the output capacitor having a value smaller than that obtained by the formula shown below. 10/16 design procedure calculation example 4. selection of diode when v in = 36 v and io = (max.) 2 a, when v in =13.2v,vo=5v,andio=1a, i rms =1 5 (13.2-5)/(13.2) 2 =0.485 5. selection of input capacitor 6. setting of oscillation frequency 8. setting of phase compensation (rc and cc) * the set values listed above are all reference values. on the actual mounting of the ic, the characteristics may vary with the routing of wirings and the types of parts in use. in this connection, it is recommended to thoroughly verify these values on the actual system prior to use. i rms =0.485a set diode rating with an adequate margin to the maximum load current. also, make setting of the rated inverse voltage with an adequate margin to the maximum input voltage. a diode with a low forward voltage and short reverse recovery time will provide high efficiency. select a diode of rated current of 2 a or more and rated withstand voltage of 36 v or more. two capacitors, ceramic capacitor c in and bypass capacitor c, should be inserted between the v in andgnd.besuretoinsert a ceramic capacitor of 1 to 10 fforthecthecapacitorc should have a low esr and a significantly large ripple current. the ripple current i rms can be obtained by the following formula: select capacitors that can accept this ripple current. if the capacitance of cin and c is not optimum, the ic may malfunction. i rms =i o vo (vin-v o )/ v in 2 referring fig. 34 and fig. 35 on the following page, select r for the oscillation frequency to be used. furthermore, in order to eliminate noises, be sure to connect ceramic capacitors of 0.1 to 1.0 f in parallel. the phase margin can be set through inserting a capacitor or a capacitor and resistor between the inv pin and the fb pin. each set value varies with the output coil, capacitance, i/o voltage, and load. therefore, set the phase compensation to the optimum value according to these conditions. (for details, refer to application circuit on page 11.) if this setting is not optimum, output oscillation may result. directions for pattern layout of pcb 1 2 3 4 5 6 7 8 arrange the wirings shown by heavy lines as short as possible in a broad pattern. locate the input ceramic capacitor cin as close to the vin-gnd pin as possible. locate the r t and c t as close to the gnd pin as possible. locate the r1 and r2 as close to the inv pin as possible, and provide the shortest wiring from the r1 and r2 to the inv pin. locate the r1 and r2 as far away from the l as possible. separate power gnd(schottky diode, i/o capacitor's gnd) and signal gnd(r t ,c t 's gnd), so that sw noise don't have an effect on signal gnd at all. design the power wire line as wide and short as possible. additional pattern for cx1 and cx2 expand compesation flexibility. fig.31 1 2 4 3 8 8 6 5 v in sw c co r3 c3 r t c t cin r1 r2 signal gnd cx2 cx1 l gnd power fb gnd gnd inv rt en bd9778hfp l o a d phase compensation setting procedure 11/16 r feedback c fb - + a (1) typical integrator (low pass filter) (2) open loop characteristics of integrator 0 a 0 -90 - 90? - 180? -180 phase [?] gain [db] f f gbw(b) - 20db/decade phase margin (a) the following section describes the stability conditions of the negative feedback system. since the dc/dc converter application is sampled according to the switching frequency, gbw (frequency at 0-db gain) of the overall system should be set to 1/10 or less of the switching frequency. the following section summarizes the targeted characteristics of this application. ~ at a 1 (0-db) gain, the phase delay is 150? or less (i.e., the phase margin is 30? or more). ~ the gbw for this occasion is 1/10 or less of the switching frequency. responsiveness is determined with restrictions on the gbw. to improve responsiveness, higher switching frequency should be provided. replace a secondary phase delay (-180?) with a secondary phase lead by inserting two phase leads, to ensure the stability through the phase compensation. furthermore, the gbw (i.e., frequency at 0-db gain) is determined according to phase compensation capacitance provided for the error amplifier. consequently, in order to reduce the gbw, increase the capacitance value. 1. application stability conditions since the error amplifier is provided with (1) or (2) phase compensation, the low pass filter is applied. in the case of the dc/dc converter application, the r becomes a parallel resistance of the feedback resistance. t oscillation frequency s graph value is typical value, oscillation frequency is necessary to consider ? 20% as dispersion. fig.35 r t vs f osc ( bd9001f ) 50 100 150 200 250 300 100 50 200 300 400 500 600 700 800 oscilating frequency setting resistance : rt [k ] oscilating frequency : fosc[khz] fig.34 r t vs f osc (bd9781hfp/bd9778f/hfp) 800 50 100 150 200 250 300 350 400 450 500 100 0200 300 400 500 600 700 oscilating frequency setting resistance : r t [k ] oscilating frequency : fosc[khz] fig.32 bd9001f reference layout pattern fig.33 bd9781hfp reference layout pattern t as shown above, design the gnd pattern as large area as possible within inner layer. t gray zones indicate gnd. co l c cin di r t r3 cx1 r1 c3 cx2 r2 c t co l c cin di cx1 r3 c3 cx2 r2 r1 r t c t point (a) fa = point (b) fa = gbw = [hz] [hz] 2rc 1 2rca 1 12/16 l c + v cc v o l r esr c v cc v o (1) lc resonant circuit (2) with esr provided fr = 1 [hz] at this resonance point, a -180? a -90? phase-delay occurs. phase-delay occurs. (3) insert feedback resistance in the c. (4) insert the r3 in integrator. c1 v o r1 r2 c2 fb inv - + a v o r1 r2 r3 c2 fb inv - + a 3. for output capacitors having low esr, such as low impedance electrolyte capacitor or os-con (1) phase compensation with secondary phase lead v o r1 c1 r2 r3 c2 fb inv - + a for output capacitors that have high esr (i.e., several ), the phase compensation setting procedure becomes comparatively simple. since the dc/dc converter application has a lc resonant circuit attached to the output, a -180? phase-delay occurs in that area. if esr component is present, however, a +90? phase-lead occurs to shift the phase delay to -90?. since the phase delay should be set within 150?, it is a very effective method but tends to increase the ripple component of the output voltage. to cancel the lc resonance, the frequency to insert the phase lead should be set close to the lc resonant frequency. the settings above have are estimated. consequently, the settings may be adjusted on the actual system. furthermore, since these characteristics vary with the layout of pcb loading conditions, precise calculations should be made on the actual system. in order to use capacitors with low esr (i.e., several tens of m), two phase-leads should be inserted so that a -180? phase-delay, due to lc resonance, will be compensated. the following section shows a typical phase compensation procedure. to set phase lead frequency, insert both of the phase leads close to the lc resonant frequency. according to empirical rule, setting the phase lead frequency f z2 with r3 and c2 lower than the lc resonant frequency fr, and the phase lead frequency f z1 with the r1 and c1 higher than the lc resonant frequency fr, will provide stable application conditions. according to changes in phase characteristics, due to the esr, only one phase lead should be inserted. for this phase lead, select either of the methods shows below: 2. for output capacitors having high esr, such as electrolyte capacitor ( ) 13/16 14/16 fig.36 equivalent circuit fig.37 typical simple construction of monolithic ic p layer e b c (pin b) transistor (npn) p n n n n gnd parasitic element gnd p + p + (pin a) gnd parasitic element (pin b) gnd b e c parasitic element p + p layer (pin a) resistor p n n n gnd parasitic element p + cautions on use 1) absolute maximum ratings an excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break d own the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. if any over rated va lues will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. furthermore, don't tu rn on the ic with a fast rising edge of v in . ( rise time << 10v / sec ) 2) gnd potential gnd potential should maintain at the minimum ground voltage level. furthermore, no terminals should be lower than the gnd potential voltage including an electric transients. 3) thermal design use a thermal design that allows for a sufficient margin in light of the power dissipation (pd) in actual operating conditions. 4) inter-pin shorts and mounting errors use caution when positioning the ic for mounting on printed circuit boards. the ic may be damaged if there is any connection er ror or if positive and ground power supply terminals are reversed. the ic may also be damaged if pins are shorted together or are shor ted to other circuits power lines. 5) operation in strong electromagnetic field use caution when using the ic in the presence of a strong electromagnetic field as doing so may cause the ic to malfunctio n. 6) inspection with set printed circuit board when testing the ic on an application board, connecting a capacitor to a pin with low impedance subjects the ic to stress. always discharge capacitors after each process or step. always turn the ic's power supply off before connecting it to, or remo ving it from a jig or fixture, during the inspection process. ground the ic during assembly steps as an antistatic measure. use similar precaution when transporting and storing the ic. 7) ic pin input (fig. 37) this monolithic ic contains p+ isolation and p substrate layers between adjacent elements to keep them isolated. p-n junctions are formed at the intersection of these p layers with the n layers of other elements, creating a parasitic diode or transistor. for example, the relation between each potential is as follows: when gnd > pin a and gnd > pin b, the p-n junction operates as a parasitic diode. when pin b > gnd > pin a, the p-n junction operates as a parasitic transistor. parasitic diodes can occur inevitably in the s tructure of the ic. the operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical da mage. accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the gnd (p substrate) vol tage to an input pin, should not be used. vin en/sync 222 k 221 k 2k vrega 139 k 145 k sw sw en vin 10k 300k 250k vin 2k 300k 50k rt vin vref vin en/sync(bd9781hfp) en(bd9778f/hfp, bd9001f) 1k vin fb vref 1k inv vin vref fb(bd9778f/hfp, bd9781hfp) inv rt fb(bd9001f) 1k vin fb vref 1k 15/16 thermal derating characteristics fig.39 fig.40 9. temperature protection (thermal shut down) circuit 8. ground wiring pattern 10. on the application shown below, if there is a mode in which v in and each pin potential are inverted, for example, if the v in is short-circuited to the ground with external diode charged, internal circuits may be damaged. to avoid damage, it is recommended to insert a backflow prevention diode in the series with v in or a bypass diode between each pin and v in . fig.35 pin backflow prevention diode bypass diode vcc it is recommended to separate the large-current gnd pattern from the small-signal gnd pattern and establish a single ground at the reference point of the set pcb, so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal gnd. prevent fluctuations in the gnd wiring pattern of external parts. this ic has a built-in temperature protection circuit to prevent the thermal destruction of the ic. as described above, be sure to use this ic within the power dissipation range. should a condition exceeding the power dissipation range continue, the chip temperature tj will rise to activate the temperature protection circuit, thus turning off the output power element. then, when the tip temperature tj falls, the circuit will be automatically reset. furthermore, if the temperature protection circuit is activated under the condition exceeding the absolute maximum ratings, do not attempt to use the temperature protection circuit for set design. single piece of ic pcb size: 70 x 70 x 1.6 mm 3 (pcb incorporates thermal via.) copper foil area on the front side of pcb: 10.5 x 10.5 mm 2 2-layer pcb (copper foil area on the reverse side of pcb: 15 x 15 mm 2 ) 2-layer pcb (copper foil area on the reverse side of pcb: 70 x 70 mm 2 ) 4-layer pcb (copper foil area on the reverse side of pcb: 70 x 70 mm 2 ) single piece of ic when mounted on rohm standard pcb (glass epoxy pcb of 70 mm x 70 mm x 1.6 mm) 10 9 8 7 6 5 4 3 2 1 0 7.3w ambient temperature 9? ta : : 5.5w 2.3w 1.4w 25 50 75 hrp7 100 125 150 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 25 05075 sop8 100 125 150 power dissipation 9? pd [ w ] power dissipation 9? pd [ w ] ambient temperature 9? ta : : bd9778f bd9001f selection of order type rohm model name bd - product no. 9778 = 36v/2a 9781 = 36v/4a 9001 = 50v/2a package type f = sop8 hfp = hrp7 taping typ e e2 = reel-type embossed carrier tape (sop8) tr = reel-type embossed carrier tape (hrp7) notes no technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of rohm co.,ltd. the contents described herein are subject to change without notice. the specifications for the product described in this document are for reference only. upon actual use, therefore, please request that specifications to be separately delivered. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. products listed in this document are no antiradiation design. appendix1-rev2.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / europe / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2008 rohm co.,ltd. the products listed in this document are designed to be used with ordinary electronic equipment or de vices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. it is our top priority to supply products with the utmost quality and reliability. however, there is always a chance of failure due to unexpected factors. therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. rohm cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the notes specified in this catalog. 21 saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix |
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